The present disclosure relates generally to image data decoding and, more particularly, to decoding image data by decoding multiple bins in parallel.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic devices often use one or more electronic displays to present visual representations of information as text, still images, and/or video by displaying one or more image frames based on image data. For example, such electronic devices may include computers, mobile phones, portable media devices, tablets, televisions, virtual-reality headsets, and vehicle dashboards, among many others. Since image data may be received from another electronic device and/or stored in the electronic device, the image data may be encoded (e.g., compressed) to reduce size (e.g., number of bits) and, thus, resources (e.g., transmission bandwidth and/or memory addresses) used to transmit and/or store image data. To display image frames, the electronic device may decode encoded image data and instruct the electronic display to adjust luminance of display pixels based on the decoded image data.
To facilitate encoding, a prediction encoding process may be used to compress image data. For example, a prediction encoding process may compress a portion of the image data by referencing another portion of the image data, thereby generating prediction encoded image data including symbols (e.g., syntax elements) that indicate the relationship between the portions of the image data. Additionally, an entropy encoding process may compress the prediction encoded image data by indicating the symbols based on frequency of occurrence in the prediction encoded image data. In this manner, the entropy encoding process may further compress the image data by generating entropy encoded image data that indicates more frequently occurring symbols using fewer bits.
The encoded image data is often includes high-quality, high-resolution video streams that are encoded via a particular standard (e.g., High Efficiency Video Coding (HEVC) (H.265)). The current discussion specifically refers to the HEVC standard, as referenced in the documents titled, “High Efficiency Video Coding (HEVC) Range Extensions text specification: Draft 7” and “Draft high efficiency video coding (HEVC) version 2, combined format range extensions (RExt), scalability (SHVC), and multi-view (MV-HEVC) extensions,” which are incorporated herein in their entirety. However, this is not intended to limit the scope to HEVC applications. Indeed, the techniques discussed herein may apply to other encoding standards.
To decode the encoded image data quickly enough for display at high frame rates, special-purpose hardware decoders may be implemented as integrated logic circuits. HEVC bitstream decoding involves entropy decoding of the bits followed by parsing of syntax elements. The challenge to achieving the above requirement comes from two aspects of the HEVC bitstream that limit opportunities for parallelization of the decode process.
First, the HEVC bitstream has embedded control information that governs the flow of the parsing process. Hence the results of decoding one syntax element govern which syntax element will be decoded next.
Second, the HEVC bitstream is arithmetically coded. Thus the HEVC bitstream undergoes an arithmetic decoding process. Arithmetic decoding is an inherently bit-serial computation process, where the results of decoding one bin impact how the next bin will be decoded. For example, HEVC arithmetic decoding involves decoding of: i. Context adaptive binary arithmetic coded (CABAC) bins, ii. Bypass coded bins, and iii. bitstream terminate bins.
The results of the parsing process impact the arithmetic decoding process, and vice versa. In other words, the parsing process and the arithmetic decoding process are interdependent. This interdependency results in added complexity to the decoding process.